Ramp-and-pedestal triggering is an improved version of synchronized-UJT-oscillator triggering. This triggering circuit is used for controlling power in an AC load and can also be applied to trigger thyristors in single-phase semiconverters or full converters.
The circuit utilizes two SCRs (Silicon-Controlled Rectifiers) connected in antiparallel.the voltage waveforms show in Figure, illustrate the operation of the circuit.
.webp "Ramp-and-pedestal triggering Circuit of Thyristors or SCR")
The circuit includes a Zener diode (Vz) which maintains a constant threshold voltage. A resistor R2 acts as a potential divider, and the wiper of R2 controls the value of the pedestal voltage (Vpd).
A diode D allows the capacitor C to be quickly charged to Vpd through the low resistance of the upper portion of R2. The wiper setting on R2 ensures that Vpd is always less than the UJT firing point voltage ηVz. When Vpd is small, the voltage Vz charges C through R. Once this ramp voltage Vc reaches ηVz, the UJT fires, and the pulse transformer transmits the voltage Vg to the gate circuits of both SCRs T1 and T2.
As a result, the forward-biased SCR T1 is turned on. The voltage Vc reduces to Vpd and then reaches zero at ωt = π. Since Vc is greater than Vpd, during the charging of capacitor C through resistor R, diode D is reverse biased and turned off. Thus, Vpd does not affect the discharge of C through the UJT emitter and the primary of the pulse transformer.
From 0 to π, T1 is forward biased and turned on, and from π to 2π, T2 is forward biased and turned on. This sequence repeats, subjecting the load to an alternating voltage V0 as shown in Figure.
By adjusting the wiper setting on R2, the pedestal voltage Vpd on C can be controlled. A low pedestal voltage across C results in a longer time for ramp charging of C to ηVz, causing a larger firing angle delay and a lower output voltage. On the other hand, a high pedestal voltage accelerates the voltage ramp charging of C through R, allowing it to reach ηVz faster, resulting in a smaller firing angle delay and a higher output voltage. This shows that the output voltage is proportional to the pedestal voltage.
The time required for the capacitor to charge from the pedestal voltage Vpd to ηVz, denoted as T, In the below equation RC is the time constant,can be calculated using the equation:
ηVz = Vpd + (Vz - Vpd)(1 - e-T/RC)
ηVz - Vpd = (Vz - Vpd)(1 - e-T/RC)
1 - e-T/RC = \(\frac{ηVz - Vpd}{Vz-Vpd}\)
-e-T/RC = \(\frac{ηVz - Vpd}{Vz-Vpd}\) - 1
e-T/RC = 1 - \(\frac{ηVz - Vpd}{Vz-Vpd}\) = \( \frac{Vz - Vpd - ηVz + Vpd}{Vz-Vpd}\) = \( \frac{Vz - ηVz)}{Vz-Vpd}\) = \( \frac{Vz(1 - η)}{Vz-Vpd}\)
both sides multiplied by algorithms,
In(e-T/RC) = \( \ln\frac{{Vz(1- \eta)}}{{Vz-Vpd}}\)----equation(1)
algorithm formula, In(xy) = y In(x), In(x/y) = In(x) - In(y), In(e) = 1
for equation(1)-----
-\( \left[\frac{T}{RC}\right]\) In(e) = In(Vz(1 - η)) - In(Vz - Vpd)
\( \frac{T}{RC}\) = In(Vz - Vpd) - In(Vz(1 - η)) = \( \ln\frac{{Vz - Vpd}}{{Vz(1- \eta)}}\)
\(T = RC \ln\frac{{Vz - Vpd}}{{Vz(1- \eta)}}\)
\(α2 = ωRC \ln\frac{{Vz - Vpd}}{{Vz(1- \eta)}}\)
Where show in figure,
ω = angular frequency of the AC waveform
α2 = firing angle delay
η = Intrinsic stand-off ratio of UJT
D1, D2, D3 and D4 = Diodes form full-wave bridge
Vpd = Pedestal voltage
Vs = Source voltage
Vc = Capacitor voltage
Vz = Voltage across zener diode
T1, T2 = Thyristors.
R = charging resistor value,
C = capacitance.
What are the advantages of ramp-and-pedestal triggering?
Some of the advantages of ramp-and-pedestal triggering are:
- It allows a wide range of control over the firing angle and output power by varying the pedestal voltage.
- It provides a more accurate and stable triggering of the thyristors by using a UJT.
- It reduces the power dissipation in the UJT by using a zener diode to limit the base voltage.
- It eliminates the need for synchronization with the source voltage as the capacitor charges and discharges according to the pedestal voltage.
- ramp-and-pedestal triggering of SCR provides precise control, reduced electrical noise, improved efficiency, enhanced circuit protection, and compatibility with control systems.
What are the disadvantage of ramp-and-pedestal triggering?
The main disadvantage of ramp-and-pedestal triggering of SCR (Silicon Controlled Rectifier) is the complexity and cost associated with its implementation. This method requires additional circuitry, including a ramp generator and a pedestal voltage source, to control the SCR's firing angle. The need for these extra components increases the complexity of the system design and adds to the overall cost of the setup.
The ramp-and-pedestal triggering technique may also introduce additional noise and instability into the circuit. The ramp generator and pedestal voltage source can be susceptible to variations in their output, leading to inaccuracies in triggering the SCR. This instability can affect the overall performance and reliability of the SCR-based system.
What are the application of ramp-and-pedestal triggering?
Some applications of ramp-and-pedestal triggering are:
- Speed control of AC motors
- Light dimming circuits
- Temperature control of heaters
- Voltage regulation of power supplies
How can I calculate the firing angle of ramp-and-pedestal triggering?
The firing angle of ramp-and-pedestal triggering can be calculated by using the following formula:
$$\alpha = \omega R C \ln \frac{V_z - V_p}{V_z (1 - \eta)}$$
where
- α is the firing angle in radians
- ω is the input angular frequency in radians per second
- R is the charging resistance in ohms
- C is the capacitor capacitance in farads
- Vz is the zener diode voltage in volts
- Vp is the pedestal voltage in volts
- η is the intrinsic stand-off ratio of the UJT (a constant between 0 and 1)
The firing angle determines the delay between the zero crossing of the input voltage and the triggering of the thyristors. A smaller firing angle means a larger output voltage and vice versa.
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